A high performance Flash-based memory system may be designed with a very high degree of parallelism. By employing more parallel execution threads or paths, the overall performance can be very high even if the low-level devices are relatively slow.
An example of a memory system using these concepts is described in U.S. 61/650,604, filed on May 23, 2012, entitled “FLASH MEMORY CONTROLLER”, which is commonly owned, and which is incorporated herein by reference.
In such a system, there are numerous hazards to data integrity: for example, coherency corruption. Data path activity may be comprised of hundreds of data segments being dispatched to numerous low-level storage devices, each data segment with a distinct storage command. A small error in such a system can lead to rampant user data loss: a catastrophic failure.